Contrast Interposer Stacking System And Method

ABSTRACT

The present description provides increased contrast between interposer and leads in a stack embodiment that employs an interposer that extends beyond a boundary or perimeter established by the leads of the constituent IC devices.

RELATED APPLICATIONS

This application is a continuation of Ser. No. 11/533,743, filed Sep.20, 2006, now U.S. Pat. No. 7,573,129, which is a continuation-in-partof U.S. patent application Ser. No. 11/452,532, filed Jun. 14, 2006, nowU.S. Pat. No. 7,375,418, which are hereby incorporated by reference.

TECHNICAL FIELD

The present invention relates to stacked integrated circuits and, inparticular, to techniques and systems directed to alignment of stackswith locations on circuit boards.

BACKGROUND

A variety of techniques are used to stack integrated circuits. Somerequire that the circuits be encapsulated in special packages, whileothers use circuits in conventional packages. Both leaded and BGA typepackaged integrated circuits (ICs) have been stacked. Although BGApackaging is becoming widely adopted, leaded packages are still employedin large volumes in low cost applications such as, for example, flashmemory. Flash memory is typically packaged in thin small outlinepackages otherwise known as TSOPs, a type of leaded packaged integratedcircuit.

When leaded packages such as TSOPs are stacked, a variety of techniqueshave been employed. In some cases, the leads alone of packaged circuitshave been used to create the stack and interconnect its constituentelements. In other techniques, structural elements such as printedcircuit boards (PCBs) are used to create the stack and interconnect theconstituent elements.

Circuit boards and rail-like structures in vertical orientations havebeen used for years to provide interconnection between stack elements.For example, in U.S. Pat. No. 5,514,907 to Moshayedi, a technique isdescribed for creating a multi-chip module from surface-mount packagedmemory chips. The devices are interconnected on their lead emergentedges through printed circuit boards oriented vertically to a carrier ormotherboard that is contacted by connective sites along the bottom ofthe edge-placed PCBs. The PCBs have internal connective rail-likestructures or vias that interconnect selected leads of the upper andlower packaged memory chips. Japanese Patent Laid-open Publication No.Hei 6-77644 discloses vertical PCBs used as side boards to interconnectpackaged circuit members of the stack. In U.S. Pat. No. 5,266,834 toNishi et al., one depicted embodiment illustrates a stack created byselective orientation of the leads of particularly configured stackelements, while in U.S. Pat. No. 5,343,075 to Nishino, a stack ofsemiconductor devices is created with contact plates having connectivelines on inner surfaces to connect the elements of the stack. Anothertechnique for stacking leaded packaged ICs with carrier structures orinterposers oriented along lead bearing sides of packaged devices suchas TSOPs is disclosed by the present assignee, Staktek Group L.P., inU.S. Pat. No. 6,608,763 to Burns et al.

Many of the previously cited and known techniques for using PCBs andsimilar interposer structures for stacking leaded packaged devices haveevolved to meet the increased connective complexity presented by, forexample, stacking memory components that have two chip enables perpackaged device. In some cases, this evolution has included use ofinterposer designs that employ four layer designs to implement the morecomplex connection strategies required by more complex devices. This hasled to complexities in via and connection strategies, however.

Higher layer count PCBs and similar interposers are more expensive anddifficult to produce than simpler designs with fewer layers. Suchconnective elements also typically exhibit wider variations across thepopulation.

Staktek Group L.P., the assignee of the present application hasdeveloped a system and method for selectively stacking andinterconnecting leaded packaged integrated circuit devices withconnections between the feet of leads of an upper IC element and theupper shoulder of leads of a lower IC element while traces thatimplement stacking-related intra-stack connections between theconstituent ICs are implemented in interposers or carrier structuresoriented along the leaded sides of the stack and which extend beyond theperimeter of the feet of the leads of the constituent ICs or beyond theconnective pads of the interposer. This leaves open to air flow, most ofthe transit section of the lower lead for cooling, but provides a lesscomplex board structure for implementation of intra-stack connections.

SUMMARY OF THE INVENTION

Interposers employed to interconnect the constituent ICs of integratedcircuit stacks exhibit areas visually distinct from the leads of theconstituent stack ICs. When interposers extend beyond the leads, itbecomes more difficult for vision systems to acquire the leads forpurposes of placing the stack in its designated location on, forexample, a circuit board. What is needed therefore, is a system andmethod for adapting stacks that employ interposers for enhanced visionsystem board population.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B depict a cross-section of a prior art circuit modulethat employs interposers (e.g., “carrier structures”, “side boards”)that implement intra-stack connections.

FIGS. 2A and 2B various views of an interposer employed in the prior artcircuit module depicted in FIGS. 1A and 1B.

FIG. 3 depicts a cross-section of a portion of circuit module thatemploys interposers that exhibit external traces on the respective upperand lower surfaces for implementing connections between two non-adjacentleads in a preferred embodiment of the present invention.

FIG. 4 depicts a plan view from below a portion of an interposer showingleads disposed on lower connective pads in accordance with a preferredembodiment of the present invention.

FIG. 5 illustrates a cross-sectional view of a portion of a circuitmodule 10 according to a preferred embodiment of the present invention.

FIG. 6 is a plan view of an exemplar interposer or carrier structureillustrating the paths of connective traces along the upper and lowersurfaces of the interposer.

FIG. 7 illustrates in cross-section, an exemplar interposer or carrierstructure in accordance with a preferred embodiment of the presentinvention.

FIG. 8 depicts a portion of a circuit module in accordance with apreferred embodiment of the present invention.

FIG. 9 is another view of a portion of a circuit module in accordancewith a preferred embodiment of the present invention.

DETAILED DESCRIPTION

The present description provides increased contrast between interposerand leads in a stack embodiment that employs an interposer that extendsbeyond a boundary or perimeter established by the leads of theconstituent IC devices. The principles of the invention may, however, beapplied to a variety of interposer and IC combinations andconfigurations with consequent advantages for board population withstacks as those of skill will recognize after appreciating thisspecification.

FIG. 1A depicts a cross-section of a portion of a prior art circuitmodule that employs interposers (e.g., “carrier structures”, “sideboards”) that implement intra-stack connections. As shown, interposersreside along the edge of the module and interconnects the feet of leadsthat emerge from first and second peripheral sides 20P1 and 20P2 of theupper IC 12 to the shoulder of leads of the lower IC 14. The ICs havewithin their respective packages integrated circuit die 24. FIG. 1B isan enlarged portion of the view of FIG. 1A. The depicted ICs aretypically thin small outline packages known as TSOPs which are a commonpackaging option for flash memory circuitry. In structures such as thatdepicted in FIGS. 1A and 1B, the interposers typically extend to aboutthe feet of the constituent ICs and any needed traces that connectnon-adjacent pads of the interposers transit through buried layers ofthe interposer.

FIGS. 2A and 2B various views of an interposer employed in the prior artcircuit module depicted in FIGS. 1A and 1B. FIG. 2A is a plan view of aprior art interposer from above and depicts with dotted lines two tracesT1 and T2 routed through buried layers in the interposer in ways thatavoid interference with vias P2 and P3, respectively. FIG. 2B depicts across-sectional view from the side of an interposer employed in theprior art module shown in FIGS. 1A and 1B. Consequently, the substantialcoincidence between the leads of the constituent ICs and the employedinterposers does not impede upwardly-directed vision system alignment.An accurate evaluation of important dimensional aspects of the modulesuch as, for example, the location of the leads may be made and thusefficient population of motherboards or other applications may proceedwith such stacks as with monolithic devices.

There are, however, reasons to construct stacks with interposers that donot coincide with the leads of the constituent ICs. As those of skillunderstand, typically only one of the constituent IC devices of a stackis enabled at a time. However, some TSOPs have two chip enable leadsthat must be signaled for device enablement. This adds complexity to theinterposer design and fabrication. Designers of stacks that employinterposers disposed between the feet of the upper IC and the shouldersof the lower IC typically try to keep the profile of the stackapproximately the same as the profile of the constituent IC devices.This objective and the need for differential enablement strategies inconnecting the upper and lower ICs typically causes designers to resortto buried layers in the interposer to implement trace connectionsbetween leads, particularly when the leads to be connected are notadjacent on the IC. This can require moving particular pins to avoidinterference between a pin that is between two pins that are to beconnected by a trace. FIGS. 2A and 2B illustrate a particular example ofthe complexity problem presented by stacking TSOP devices withfeet-to-shoulder interposers, each disposed along a leaded side of theconstituent devices where profiles for the resulting stack arecommensurate with the profiles of the constituent ICs. Consequently, asshown in FIGS. 2A and 2B, blind vias such as those identified as BV1 andBV2 are connected to traces T1 and T2 and then to lower pads LP3 andLP4. Thus, signals at LP3 are conveyed to upper pads UP3 and UP1 whilesignals at LP4 are conveyed to UP4 and UP2. Traces T1 and T2 are,however, implemented at layers 2 and 3 respectively, of the depictedfour layer board (showing layers L1, L2, L3, and L4). Layers 2 and 3are, however, buried in the interposer. As those of skill willrecognize, PCB materials that may be used as interposers in suchapplications can be devised with multiple buried metal layers toimplement trace connections between vias but such structures are likelyto exhibit thicker profiles and are complex to manufacture efficientlyand may have wider variations from instance to instance.

As discussed, for many reasons, designers of this category of stack havetypically tried to stay within profile limits thus resulting inimplementation of carrier structures or interposers that exhibit themore complex designs alluded to and an example of which was justdescribed. However, profile requirements are typically intended, amongstother things such as vision system adaptation, to preserve mountingboard area. Thus, if a profile constraint is intended to preservemounting board area but is not devised to limit cantilever designs thatmay exceed the profile but only above the surface of the mounting board,a wider interposer above mounting circuit board level may, in somecases, be employed to preserve board mounting space and still implementconnections in stacks which retain the foot to shoulder interposerconstructions that keep a substantial portion of the leads open. Thismay still leave open a potential problem with vision system placement ofsuch modules on circuit board applications.

FIG. 3 depicts a cross-section of a portion of circuit module 10 thatemploys interposer 40 that exhibits external traces 60 and 62 on therespective upper and lower surfaces 45 and 47 of interposer 40 forimplementing, for example, connections between two non-adjacent leads.As shown, module 10 is created with upper IC 12 and lower IC 14. Each ofICs 12 and 14 are, in the depicted preferred embodiment, plasticencapsulated memory circuits disposed in thin small outline packagesknown as TSOPs. Other package types may be used with the presentinvention as well as packaged circuits other than memories, but, asdescribed here as preferred examples, the invention is advantageouslyimplemented with memories in TSOP packaging. Flash memory circuitsimplemented in TSOP packaging are one type of preferred constituent ICs12 and 14. As shown in FIG. 3 as to lower IC 14, but present in both IC12 and 14 of module 10, each IC has a lower surface 16, upper surface 18and periphery. In this FIG. 3, there is depicted an air gap 21 betweenIC 12 and IC 14 although a heat transference material or adhesive(thermally conductive being preferred) may reside between the ICs asindicated in later FIG. 5 with reference 34.

As depicted in FIG. 3, emergent from package peripheral wall or edge20P1, plural leads, one of which is illustrated as lead 22, provide aconnective pathway for the electronics of the circuitry chip embeddedwithin plastic body 27 of exemplar IC 12. Those of skill will note thatin a typical embodiment, the leads are emergent from each of twoperipheral sides 20P1 and 20P2 of the respective IC. There are, however,some packages that may have leads emergent from greater or fewer numbersof peripheral sides.

Lead 22 of upper IC 12 is shown as having foot 26 and shoulder 28 andtransit section 30 but similar features may be identified in lead 22 oflower IC 14. Shoulder 28 can extend from and include the planar part oflead 22 emergent from peripheral wall 20P (i.e., the “head” of theshoulder identified by reference 31) to the end of the curvature intotransit section 30. As leads 22 emerge from the package periphery, asupportive shelf or plane is created or defined (respectively) by theheads of the plurality of leads on a side. These features of lead 22 arepresent in conventional TSOP packaged memory circuits such as flashmemory available from most major suppliers of packaged memories. Foot 26is provided to allow the mounting of the TSOP IC on the surface of aprinted circuit or other carrier and signal transit board and hasterminus 25. The termini 25 of the feet of the plural leads 22 define aline SOL that coincides with the profile for the ICs as well as stackedmodule 10 at the level of the circuit board. In FIG. 3, circuit module10 is shown mounted on circuit board 42.

Shoulder 28 arises from providing foot 26 for surface mount connectionof the IC, while transit section 30 of lead 22 connects shoulder 28 withfoot 26. In practice, lead 22 and, in particular, transit section 30 aresurfaces from which heat from the internal chip(s) of the TSOP isdissipated by local air convection. Transit section 30 is often asubstantially straight path but may exhibit curvature or angles.

Interposer or carrier structure 40 is shown in FIG. 3 as beinginterposed between shoulder 28 of lead 22 of lower IC 14 and foot 26 oflead 22 of upper IC 12. In a preferred embodiment, interposer 40 hasupper and lower substantially planar surfaces 45 and 47, respectively.Upper surface 45 bears a row of plural upper connective elements 44 andlower surface 47 bears a row of plural lower connective elements 46.These elements 44 and 46 are shown as resting upon upper and lowersurfaces 45 and 47 of interposer 40, respectively, but as those of skillwill recognize, these elements or pads may be embedded into thosesurfaces and in typical applications will be implemented as pads.

In module 10, upper connective elements 44 are disposed beneath the feetof the leads of IC 12 and the lower surface 47 is placed along the planeof heads 31 of selected leads of lower IC 14 as shown in FIG. 3. Carrierstructure or interposer 40 is, in a preferred embodiment, printedcircuit board material or other carrier material disposed betweencorresponding leads of constituent elements of module 10. Otherstructures that provide connective elements in an insulative bed orcarrier may be employed as interposer or carrier structure 40.

In a preferred embodiment, two interposers 40 are typically employed ina module 10 comprised from two TSOP memory devices. One interposer 40 isdisposed along one leaded periphery of module 10, while anotherinterposer 40 is disposed in conjunction with an opposite leadedperiphery of the module. The same principles may be applied to stackswhere the constituent ICs have more or fewer than two leaded sides.

Imaginary line SOL may be defined by the terminal ends 25 of the feet 26of leads 22 of upper IC 12. As those of skill know, a TSOP IC has aplurality of leads, and the plural ends of the feet of those pluralleads are aligned in a row. That row line of the ends or termini 25constitute line 50L.

As those of skill will recognize, when there is not coincidence betweenthe widest lateral extent of an interposer and the termini of leads ofthe constituent ICs connected with the interposer, vision systemequipment may not be able to adequately or accurately acquire thecoordinates of lead termini 25 for purposes of board population. Forexample, as shown in FIG. 5, interposer 40 extends beyond the termini 25of feet 26 to imaginary line 40M as shown. The assignee of the presentinvention has recognized that when no provision is made to enhance thecontrast between the leads 22 and interposer 40, vision systemacquisition of leads 22 for board population purposes becomesproblematic when the widest lateral extent for interposer 40 (identifiedby line 40M) exceeds line 50L that identifies the termini 25 of feet 22.

FIG. 4 depicts a plan view from below of a portion of an interposer 40and leads 22 ₁-22 ₄ (e.g., feet 26) as disposed on lower connectiveelements 46 ₁-46 ₄. Connective trace 62 is shown extending from lowerconnective elements 46 ₁ to lower connective element 46 ₄. Illustrativevia 64 is shown associated with lower connective element 46 ₄.

A portion of interposer 40 is shaded to represent dark portion 40D.Another portion of interposer 40 represents light portion or area 40LCof interposer 40 and separation between areas 40D and 40LC is indicatedwith imaginary line K. Further, dark areas 40D need not be contiguousfor a particular interposer and may be localized in relation toparticular feet of the lower one of the constituent ICs of the moduleand therefore, may be implemented by plural selected dark areas 40D on asingle interposer lower side. Imaginary line K should be closer to body27 of the constituent ICs than the termini 25 of leads 22 (i.e., line50L). As shown in later FIG. 5, interposer 40 is also allocated into twosections, an inner section 401 toward the body 27 of IC 12 and an outeror external section 40EX. The line between interposer sections 40I and40EX is line 50L which is coincident with the termini of leads 22. Darkarea or portion 40D may be realized with ink or a darker solder mask,just as examples, as shown in FIG. 5. A darker dye may also be employedin the fabrication of interposer 40. The resulting higher contrastbetween leads 22 and dark area 40D improves vision system performance byallowing vision equipment to more easily acquire the coordinates offeatures of leads 22, for example, such as termini 25.

FIG. 5 illustrates a cross-sectional view of a portion of a circuitmodule 10 according to a preferred embodiment of the present invention.Interposer or carrier structure 40 is soldered into place as shown bysolder 35 that improves the connection of foot 26 of upper IC 12 withupper connective element 44 of carrier structure 40. Upper and lower ICs12 and 14 are physically connected together with adhesive 34 in thisdepicted embodiment.

In the embodiment shown in FIG. 5, connective elements 44 and 46 aretypically etched pads although other means of connection are known inthe art. Solder 35 is also shown providing certain connection betweenlead 22 of lower IC 14 and lower connective element pad 46 of interposeror carrier structure 40. As shown, termini 25 of leads 22 establish line50L.

Imaginary line K identifies separation between dark portion 40D andlighter portion 40LC. As shown, line K is closer to ICs of module 10than is imaginary line 50L and, in particular, is closer to body 27 ofthe lower IC of the module than is line 50L. Those of skill willrecognize that imaginary line K need not be a straight line.

Portion 40LC is more reflective of light than dark portion 40D. Alongthe lower part of interposer 40 and covering, in this embodiment, partsof exposed lower surface 47, trace 62, and part of lower connectiveelements 46 (as shown in earlier FIG. 4) contrast layer 52 realizes darkportion 40D of interposer 40 in the depicted embodiment.

Other modes of realizing dark portion 40D can include use of differentdye or colors in PCB employed to fabricate interposer 40. When color ordye is embedded in PCB material to realize dark portion 40D ofinterposer 40, contrast layer 52 will either not be visible in across-sectional view due to its integration into the material ofinterposer 40 or it will be so small as to be indiscernible incross-sectional view. When ink or solder mask material is employed tocreate dark portion 40D of interposer 40, it will typically not have therelative dimensions of contrast layer 52 as shown in FIG. 5 where suchcontrast layer 52 is dimensionally enhanced for heuristic purposes inthe cross-sectional view.

FIG. 6 is a plan view from above of an exemplar interposer or carrierstructure 40 depicting the paths of connective traces 60 along uppersurface 45 of interposer 40 and connective trace 62 (shown in dottedline) along lower surface 47 of interposer 40. As those of skill willrecognize, traces 60 and 62 are composed from conductive (typicallymetal) layers on the upper and lower surfaces respectively of interposer40.

FIG. 7 further illustrates in cross-section, an exemplar interposer orcarrier structure 40. Thus, with an interposer that can implementconnections between non-adjacent leads or connective elements with oneor more traces that extend into section 40EX, a simple construction maybe adopted for interposer 40 with surface metal layers that expresstraces such as exemplar traces 60 and 62.

Upper and lower connective elements 44 and 46 are connected to eachother in the embodiment shown in FIG. 7 through plated through holes orvias 64 typically drilled in the PCB (where PCB is the support materialfor interposer 40) during fabrication. The use of vias to connectconductive planes or traces in PCB technology is well known to those ofskill in the art. In a preferred embodiment, vias 64 may also be cutthrough length-wise to create a castellation-like structure. Otherconnectives besides vias (e.g., traces) may be used to conduct signalsbetween upper and lower connective elements 44 and 46.

Conductive layers L1 and L2 as shown in FIG. 7 on the upper and lowersurfaces of interposer 40 are preferably etched to create theappropriate pattern for the upper and lower connective elements 44 and46, respectively, as well as traces 60 and 62.

Although the present invention has been described in detail, it will beapparent that those skilled in the art that the invention may beembodied in a variety of specific forms and that various changes,substitutions and alterations can be made without departing from thespirit and scope of the invention. The described embodiments are onlyillustrative and not restrictive and the scope of the invention is,therefore, indicated by the following claims.

1. A circuit module comprised of: first and second leaded packagedintegrated circuits in stacked disposition with the first leaded packagebeing disposed above the second leaded package, each of which first andsecond leaded packaged integrated circuits having a body emergent fromwhich are leads that each have a shoulder and foot, the shoulders eachhaving a head; a first interposer for electrical connection between thefirst and second leaded packaged integrated circuits, the firstinterposer having a dark portion and a light portion delineable with animaginary line K, with the light portion being more reflective of lightthan is the dark portion and the first interposer having an externalsection and an internal section disposed on different sides of a line Ldefined by termini of a plurality of the feet of the leads of the firstleaded packaged integrated circuit, the external section of the firstinterposer being further from the first packaged integrated circuit thanis the internal section, and imaginary line K being closer to the bodyof the second packaged integrated circuit than is line L.
 2. The circuitmodule of claim 1 in which the dark portion of the first interposer isrealized with a contrast layer.
 3. The circuit module of claim 1 inwhich the dark portion of the first interposer is realized with coloredPCB material.
 4. The circuit module of claim 1 in which the dark portionof the first interposer is realized with dyed PCB material.
 5. Thecircuit module of claim 1 in which the first and second leaded packagedintegrated circuits are flash memory devices.
 6. The circuit module ofclaim 1 further comprising: a second interposer for electricalconnection between the first and second leaded packaged integratedcircuits, the second interposer having a dark portion and a lightportion delineable with an imaginary line K with the light portion beingmore reflective of light than is the dark portion and the secondinterposer having an external section and an internal section disposedon different sides of a line L defined by termini of a plurality of thefeet of the leads of the first leaded packaged integrated circuit, theexternal section of the second interposer being further from the firstpackaged integrated circuit than is the internal section, and imaginaryline K being closer to the body of the second packaged integratedcircuit than is line L.
 7. The circuit module of claim 1 in which afirst trace extends onto the external section of the first interposer.8. The circuit module of claim 1 in which the first trace connects twonon-adjacent ones of upper or lower connective elements of the firstinterposer.
 9. The circuit module of claim 6 in which thermallyconductive adhesive is disposed between the first and second leadedpackaged integrated circuits.
 10. A circuit module comprising: an upperintegrated circuit and a lower integrated circuit, each integratedcircuit having a body having an upper surface, a lower surface, and aperiphery emergent from which are a plurality of leads each having ashoulder and a foot having a terminus; two carrier structures, eachdisposed on a peripheral side of the module between selected feet of theupper integrated circuit and selected shoulders of the lower integratedcircuit to distance the upper integrated circuit above the lowerintegrated circuit, each of the two carrier structures having aninternal section and an external section delineated by an imaginary lineL coincident with the termini of the feet of the upper integratedcircuit and each of the two carrier structures having on theirrespective lower sides, a dark area and a light area, the delineationbetween which areas being disposed closer to the body of the lowerintegrated circuit than is imaginary line L.
 11. The circuit module ofclaim 10 in which the integrated circuits are TSOP packaged memorycircuits.
 12. The circuit module of claim 10 in which the integratedcircuits are flash memory circuits.
 13. The circuit module of claim 10in which the carrier structures are comprised of printed circuit boardmaterial.
 14. The circuit module of claim 10 in which thermallyconductive material resides in the space between the upper and lowerintegrated circuits.
 15. The circuit module of claim 10 in which thespace between the upper and lower integrated circuits is an air gap. 16.The circuit module of claim 10 in which the two carrier structures areetched printed circuit board patterned to connect a no-connect one ofthe leads of the lower integrated circuit with an active lead of theupper integrated circuit.
 17. A circuit module comprising: first andsecond leaded packaged integrated circuits stacked one above the otherand each having a body with peripheral sides and leads emergent from atleast one of the peripheral sides, the leads having feet each of whichfeet having a terminus; an interposer disposed between the leads of thefirst leaded packaged integrated circuit and the leads of the secondleaded packaged integrated circuit, the interposer having a first sideand a second side and having upper and lower connective elementsrespectively disposed along the first and second substantially planarsurfaces of the interposer, at least a first area of the secondsubstantially planar surface of the interposer being dark relative to asecond area of the second substantially planar surface of theinterposer.
 18. The circuit module of claim 17 in which the first areaof the second substantially planar surface of the interposer is coveredwith a contrast layer.
 19. The circuit module of claim 18 in which thecontrast layer is a layer of ink.
 20. The circuit module of claim 19 inwhich the contrast layer is a solder mask.